Semiconductor manufacturing refers to the process of fabricating complete chips on wafers through a series of complex steps, where each chip can perform specific functions. The processes involved vary depending on the type of chip product. This article briefly lists some of the semiconductor processes that may be involved in semiconductor manufacturing.
I. What is the Boundary Between Semiconductor Manufacturing and Packaging?
The goals of semiconductor manufacturing and packaging are different. Semiconductor manufacturing (Front-End) aims to produce bare wafers with complex circuit patterns, which must be processed in a highly controlled cleanroom environment to prevent dust from affecting the intricate circuit structures. In contrast, packaging (Back-End of Line) aims to protect the bare chip and enhance its physical strength, environmental durability, and other properties. Typically, wafer thinning is used as the dividing line between manufacturing and packaging. After thinning, the wafer is shipped from the wafer fab to the packaging factory, marking the end of the semiconductor manufacturing process.
II. What are the Process Differences for Different Chip Products?
A chip is a broad concept and can be subdivided into many types. Generally, chips can be categorized into logic chips (such as CPUs, GPUs), memory chips (such as DRAM, NAND, Flash), analog and mixed-signal chips, power devices, RF chips, sensor chips, and more. Different types of chip products, depending on their applications and functional requirements, use different design principles, process standards, and material choices. For example, advanced process nodes like 5nm and 7nm are typically used for logic chips, while for RF chips, processes such as SAW and BAW are not measured by line width. Additionally, while memory chips are primarily based on 12-inch wafers, third-generation semiconductors, due to the limitations of SiC substrates, commonly use 4-inch or 6-inch wafers.
Ⅲ. Semiconductor manufacturing process classification
1). Photolithography: Includes coating, exposure, development, and baking processes.
· Coating: The photoresist is evenly applied to the surface of the silicon wafer to prepare for the subsequent photolithography process. Typically, a spin coating technique is used to ensure uniformity of the resist layer and the desired film thickness. After coating, the wafer undergoes a soft bake to remove solvents, followed by exposure and development to transfer the pattern. Finally, a hard bake is performed to enhance the stability of the resist layer.
· Exposure: After the photoresist is applied, the silicon wafer is exposed to ultraviolet (UV) or deep ultraviolet (DUV) light in specific areas. A photomask is used to transfer the design pattern onto the photoresist. The reactivity of the photoresist changes depending on the intensity of the exposure light, and the unexposed areas will be removed in the subsequent steps.
· Development: After exposure, the wafer is immersed in a developer solution, which dissolves and removes the unexposed photoresist, leaving the pattern from the exposed areas. This step determines the clarity and precision of the photolithographic pattern.
· Baking: After exposure and development, the silicon wafer typically undergoes two baking treatments. Soft Bake is used to remove solvents from the photoresist, curing the resist layer and ensuring its adhesion. Hard Bake further enhances the stability and etch resistance of the resist layer, preparing it for subsequent steps such as etching.
2). Dry Processes:
· Deposition: This process is used to deposit a thin film on the surface of the silicon wafer, typically for forming conductive, insulating, or semiconductor layers. Deposition techniques can be divided into PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), and ALD (Atomic Layer Deposition).
PVD includes methods such as Evaporation, Sputtering, and Pulsed Laser Deposition (PLD).
CVD includes techniques like Plasma-Enhanced CVD (PECVD), Low-Pressure CVD (LPCVD), Metal-Organic CVD (MOCVD), MPCVD, Laser CVD, APCVD, HT-CVD, UHV CVD, and more.
· Dry Etching: Dry etching removes unwanted areas from the material surface through gas reactions or plasma interactions, creating the desired pattern on thin films or silicon wafers. Unlike wet etching, dry etching does not involve liquid solutions but instead uses gases or plasma in a vacuum environment, offering higher precision and better pattern control.
Dry etching can be divided into physical etching, chemical etching, and physico-chemical etching. Physical etching includes Ion Beam Etching (IBE), chemical etching includes plasma ashing, and physico-chemical etching includes methods such as ICP-RIE, CCP-RIE, ECR-RIE, and DRIE.
Epitaxy: Epitaxy processes include Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), and Chemical Beam Epitaxy (CBE).
· Ion Implantation: Ion implantation is mainly used to inject specific impurity elements (such as phosphorus, boron, arsenic, etc.) into the surface of the silicon wafer to alter the electrical properties of the silicon material. This process is widely applied in doping, forming PN junctions, and adjusting device performance. Ion implantation can be categorized into high-energy ion implantation, low-energy ion implantation, high-dose ion implantation, high-throughput ion implantation, and high-mass molecular ion implantation.
· Diffusion: Diffusion is a process in which dopants (such as phosphorus, boron, etc.) move from a solid-source material into the silicon wafer through heat energy. The goal of diffusion is to uniformly distribute the dopant elements within a specific depth range of the silicon wafer to change its electrical conductivity and form PN junctions. Diffusion processes can be divided into gas-source diffusion, liquid-source diffusion, solid-source diffusion, and pre-deposition diffusion.
· Annealing: Annealing is a process that optimizes material properties through heating and holding for a period of time. It is typically used to repair crystal defects formed during manufacturing, reactivate dopant elements, and optimize material structures. Annealing can be further categorized into furnace annealing, rapid thermal annealing, laser annealing, and plasma annealing.
3). Wet Process:
Wet etching is a process that uses chemical solutions to remove unwanted areas from the material surface. It is commonly used to remove metals, oxides, or other thin film materials, and is typically suitable for large-area, uniform-depth etching. The advantages of wet etching are its simplicity and low cost, but its precision is generally lower compared to dry etching.
· Cleaning: Cleaning is a fundamental and critical step in semiconductor manufacturing, used to remove contaminants, impurities, and residues from the silicon wafer surface to ensure the quality of the subsequent processes. Common cleaning processes include acid cleaning, alkaline cleaning, deionized water cleaning, and ultrasonic cleaning.
· Electroplating: Electroplating is a process where metal ions are reduced and deposited onto the silicon wafer surface using an electric current. It is commonly used to form metal layers (such as copper and electroless nickel) for interconnections, contacts, and protection. Electroplating is typically used in metal interconnects and metal protective layers.
· Electroless Plating: Electroless plating is a deposition process that does not rely on external current. It uses chemical reduction reactions to reduce metal ions and deposit a metal layer on the silicon wafer surface. Unlike electroplating, electroless plating can be performed without electrodes, making it suitable for plating complex shapes and non-conductive surfaces. Common electroless plating materials include electroless copper and electroless nickel.
· Chemical Mechanical Planarization (CMP): CMP is a planarization process that combines both chemical and mechanical actions to remove uneven materials from the silicon wafer surface, smoothing it out. CMP uses a polishing pad and chemical liquids (usually a mixture of abrasive and chemical etching solutions) to remove high and low areas on the surface. It is commonly used to remove multiple thin films, smooth surfaces, and eliminate excess plating layers.
Wet Processes are typically simpler and more cost-effective compared to high-precision dry processes (such as plasma etching or CVD). They are capable of uniformly processing large areas of silicon wafers, making them suitable for mass production. However, wet etching generally offers lower precision and selectivity when dealing with fine patterns, especially in the etching of structures with complex geometries, compared to dry etching.
